Most semiconductor devices including a dynamic random access memory (DRAM) use internal voltages generated from external voltages, e.g., a power supply voltage VDD and a ground voltage VSS. Generally the internal voltages are generated by using the external voltages and a reference voltage having a target level of the internal voltage through a charge pumping method or a voltage down converting method. In case of DRAM, voltages such as a high voltage VPP and a bulk bias voltage VBB are generated through the charge pumping method. Further, voltages such as a core voltage VCORE and a bit line precharge voltage VBLP are generated through a voltage down converting method.
The high voltage VPP has a higher voltage level than the power supply voltage VDD and is usually used for driving a word line. The bulk bias voltage VBB has a lower voltage level than a ground voltage VSS. The bulk bias voltage VBB is used for a cell transistor in DRAM to increase a data retention time of a unit cell including the cell transistor.
FIG. 1 is a block diagram of a conventional bulk bias voltage generator.
The conventional bulk bias voltage generator includes a bulk bias voltage (VBB) detector 10, an oscillator 20, a pump controller 30, and a charge pump 40. The VBB detector 10 outputs a pump enable signal BBEB based on a reference voltage VREFB and the bulk bias voltage VBB fed back from a DRAM. The reference voltage VREFB is usually generated by a band gap circuit and has a target voltage level of the bulk bias voltage VBB. The oscillator 20 performs an oscillating operation with a predetermined frequency in response to the pump enable signal BBEB to output an oscillation signal OSC. The pump controller 30 receives the oscillation signal OSC and generates a pump control signal PUMP_CTRL. The charge pump 40 performs a pump operation in response to the pump control signal PUMP_CTRL to generate the bulk bias voltage VBB.
After a voltage level of the power supply voltage VDD is stabilized to a predetermined voltage level, the internal voltage generators, including the bulk bias voltage VBB generator, start to generate internal voltages. Before the bulk bias voltage VBB generator is enabled, the bulk bias voltage VBB has a voltage level substantially the same as that of the ground voltage VSS level. The VBB detector 10 detects the voltage level of the bulk bias voltage VBB and activates the pump enable signal BBEB. The oscillator 20 starts to perform the oscillating operation in response to the pump enable signal BBEB and outputs the oscillation signal OSC having the predetermined frequency. The pump controller 30 activates the pump control signal PUMP_CTRL in response to the oscillation signal OSC. The above mentioned operations for pumping the bulk bias voltage VBB are repeatedly performed until the voltage level of the bulk bias voltage VBB reaches the target level which is determined by the reference voltage VREFB.
Meanwhile, the conventional VBB detector 10 includes a normal detector, a modulation detector. The normal detector detects the constant voltage level of the bulk bias voltage VBB without concerning temperature variations. The modulation detector detects the voltage level of the bulk bias voltage VBB with linearly depending on the temperature variation. The conventional VBB detector 10 employs one of outputs of the normal detector and the modulation detector by using a metal option.
FIG. 2 is a schematic circuit diagram of the VBB detector shown in FIG. 1.
The VBB detector 10 includes a VBB normal detector 10A, a VBB modulation detector 10B, a selection unit 10C. The VBB normal detector 10A detects a voltage level of the bulk bias voltage VBB without regarding to temperature variation and outputs a normal detection value DET_N. The VBB modulation detector 10B detects the voltage level of the bulk bias voltage according to temperature variation and outputs a modulated detection value DET_T. The selection unit 10C selects one of the normal detection value DET_N and the modulated detection value DET_T according to a metal option and outputs the selected one as the pump enable signal BBEB.
The VBB normal detector 10A includes two PMOS transistors P1 and P2 serially connected each other and a first inverter INV1. The first PMOS transistor P1 connected between a reference voltage VREFB terminal and a first node NODE_1. The first PMOS transistor P1 receives the ground voltage VSS through its gate. Further, a bulk of the first PMOS transistor P1 is connected to the reference voltage VREFB terminal. The second PMOS transistor P2 is connected to the first node NODE_1 and a ground voltage VSS terminal. The second PMOS transistor P2 receives the bulk bias voltage VBB through its gate. Further, a bulk of the second PMOS transistor P2 is connected to the reference voltage VREFB terminal. The first inverter INV1 receives voltage loaded at the first node NODE_1 to thereby output as the normal detection value DET_N. The first inverter INV1 receives a voltage loaded at the first node NODE_1 and outputs the normal detection value DET_N.
The VBB normal detector 10A detects a level of the bulk bias voltage VBB by using a resistance difference of the first and the second PMOS transistors P1 and P2. In detail, when an absolute value of the voltage level of the bulk bias voltage VBB is small, a resistance of the second PMOS transistor P2 increases. Accordingly, the voltage level of a voltage loaded at the first node NODE_1 is higher than a switching point of the first inverter INV1 and, therefore, the normal detection value DET_N becomes a logic low level. Further, when the absolute value of the voltage level of the bulk bias voltage VBB is large, the resistance of the second PMOS transistor P2 decreases. Hence, the voltage level of the voltage loaded at the first node NODE_1 is lower than the switching point of the first inverter INV1 and, therefore, the normal detection value DET_N becomes a logic high level. In an embodiment of the present invention, the switching point of the first inverter INV1 is set to have a half level of the reference voltage VREFB.
As mentioned above, the VBB detector 10 selects one of the normal detection value DET_N and the modulated detection value DET_T and outputs the selected one as the pump enable signal BBEB. Therefore, in case that the metal option is set to select the normal detection value DET_N as the pump enable signal BBEB, the pump enable signal BBEB has the same logic level with the normal detection value DET_N. That is, when the normal detection value DET_N has the logic low level, the pump enable signal BBEB is activated as a logic low level. In response to an activation of the pump enable signal BBEB, the VBB pumping unit 20 performs a pumping operation and, therefore, the absolute value of the voltage level of the bulk bias voltage VBB increases. When normal detection value DET_N has the logic high level, the pump enable signal BBEB is inactivated as a logic high level. In response to an inactivation of pump enable signal BBEB, the VBB pumping unit 20 stops performing the pumping operation and, therefore, the absolute value of the voltage level of the bulk bias voltage VBB decreases. That is, the bulk bias voltage VBB has a constant voltage level.
The VBB modulation detector 10B includes a third PMOS transistor P3, an NMOS transistor N1, and a second inverter INV2. The third PMOS transistor P3 and the NMOS transistor N1 are serially connected each other between the reference voltage VREFB terminal and a bulk bias VBB terminal. The third PMOS transistor P3 is connected between the reference voltage VREFB terminal and a second node NODE_2. The third PMOS transistor P3 receives the ground voltage VSS through its gate. A bulk of the third PMOS transistor P3 is connected to the reference voltage terminal VREFB. The NMOS transistor N1 is connected to the second node NODE_2 and the bulk bias voltage VBB terminal. The NMOS transistor N1 receives the reference voltage VREFB through its gate. A bulk of the NMOS transistor N1 is connected to the bulk bias voltage VBB terminal. The second inverter INV2 receives a voltage loaded at the second node NODE_2 to thereby output as the modulated detection value DET_T.
The VBB modulation detector 10B detects the level of the bulk bias voltage VBB by using a resistance difference of the third PMOS transistor P3 and the NMOS transistor N1. In detail, when an absolute value of the voltage level of the bulk bias voltage VBB is small, a resistance of the NMOS transistor N1 increases. Accordingly, the voltage level of a voltage loaded at the second node NODE_2 is higher than a switching point of the second inverter INV2 and, therefore, the modulated detection value DET_T becomes a logic low level. Further, when the absolute value of the voltage level of the bulk bias voltage VBB is large, the resistance of the NMOS transistor N1 is decreases. Hence, the voltage level of the voltage loaded at the second node NODE_2 is lower than the switching point of the second inverter INV2 and, therefore, the modulated detection value DET_T becomes a logic high level.
An operation of the VBB modulation detector 10B is dependent on temperature because a resistance of a PMOS transistor decreases more rapidly than that of an NMOS transistor as temperature decreases. That is, as temperature decreases, the absolute value of the voltage level of the bulk bias voltage VBB decreases because the resistance of the third PMOS transistor P3 more rapidly decreases than that of the NMOS transistor N1. In the same way, as the temperature increases, the absolute value of the bulk bias voltage VBB is increases.
FIG. 3 is a graph showing the voltage levels of the normal detection value DET_N and the modulated detection value DET_M respectively output from the VBB normal detector 10A and the VBB modulated detector 10B shown in FIG. 2.
The voltage level of the bulk bias voltage VBB detected by the VBB normal detector 10A has a constant voltage level without considering a temperature variation. The voltage level of the bulk bias voltage VBB detected by the VBB modulation detector 10B linearly varies according to the temperature variation. That is, as the temperature decreases, the absolute value of the voltage level of the bulk bias voltage VBB decreases.
When the VBB normal detector 10A is used at a high temperature, a data retention time of a unit cell increases. However, when the VBB normal detector 10A is used at a low temperature, time for writing a data into the unit cell increases. When the VBB modulation detector 10B is used to detect the voltage level of the bulk bias voltage VBB, it is possible to increase the data retention time of the unit cell for a high temperature environment and to decrease the time taken for writing a data into the unit cell. However, because the voltage level of the bulk bias voltage VBB linearly changes according to the variation of the temperature, the absolute value of the voltage level of the bulk bias voltage VBB has too high value or too low value when the temperature is extremely low or high.